Memory in Practice: Organization, Caches, Alignment, ROM & Storage

Memory in Practice: Organization, Caches, Alignment, ROM & Storage

This page explains how modern memory works in practice: how dynamic RAM is organized, why caches are necessary, how alignment affects performance, and how ROM and storage devices differ from RAM.

DRAM organization and access time

Dynamic RAM (DRAM) is arranged in a grid of rows and columns.

• To read a bit, a whole row (often thousands of bits) must first be activated.
• After activation, bits in that row can be read quickly in a burst.
• Opening a new row is slower, which creates variability in access times.

This explains why main memory is relatively slow compared to the CPU. Reading consecutive addresses is faster than random addresses because the row stays open.

Caches

To bridge the gap between CPU speed and DRAM speed, computers use static RAM (SRAM) caches.

• L1 cache: smallest, fastest, directly connected to the CPU.
• L2 and L3 caches: larger, slower, but still much faster than DRAM.
• Cache keeps recently used data, often following a replacement strategy such as least recently used (LRU).

Because caches are limited in size, cache misses force the CPU to fetch from slower DRAM.

Non-uniform memory access (NUMA)

In multiprocessor systems, not all CPUs are equally close to all memory modules.

• Local memory is faster for a given processor.
• Remote memory access is slower.

This design is called non-uniform memory access and is common in modern multi-socket servers.

Access width and byte addressing

Memory is usually accessed in units larger than a single bit.

• 8-bit systems: bytes
• 16-bit systems: words
• 32-bit systems: doublewords
• 64-bit systems: quadwords

Convention: every byte has its own address, regardless of the CPU word size.

Memory alignment

A memory access is aligned when its starting address is divisible by the access width.

• Example: a 4-byte word must start at an address divisible by 4.
• Misaligned access may require multiple memory operations.

CPU behavior varies:

• On x86: misaligned access is allowed but slower.
• On ARM: often forbidden, causing errors unless special instructions are used.

Programming languages such as C align data structures automatically to avoid these problems.

ROM and firmware

Read-only memory (ROM) retains content without power.

• Stores essential startup code, such as BIOS or UEFI.
• Embedded systems may store all code in ROM.
• Variants include PROM (written once), EPROM (erasable with UV light), and EEPROM (electrically erasable).

Firmware updates are critical for security. Devices with fixed ROM can remain vulnerable if flaws are discovered.

Storage devices

Not all memory is random access. Examples of storage:

• Hard disks: mechanical rotation and head positioning determine access.
• Solid state drives: store data in blocks, erased and written as units.
• Magnetic tape: sequential medium, slow for direct access but useful for large backups.

These devices are usually called storage rather than memory because their access patterns and speeds are fundamentally different from RAM.